Elad0708
New Contributor
1 year agoDpX4 Simulation
I Created design based on DPX4 5.4GHz. The example design includes 'dp_gxb_sysclk' module. According to Ip generation the reference clock supposed to be 150Mhz. I created simulation based on this design and it seems that the pll doesn't lock and no ref_clock or sys_clock is driven at the pll outputs. I will appricate If I can get help on this subject.
The device is Aglilex-7.
Best Regards,
Elad Rotem