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Elad0708's avatar
Elad0708
Icon for New Contributor rankNew Contributor
1 year ago

DpX4 Simulation

I Created design based on DPX4 5.4GHz. The example design includes 'dp_gxb_sysclk' module. According to Ip generation the reference clock supposed to be 150Mhz. I created simulation based on this des...
Fpga Devkit
Farabi's avatar
Farabi
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hello,


We will look into your PLL setting first.

  1. Do you have design example we can check your PLL parameters?
  2. If you reduce the output clock speed- can it lock?


possible cause PLL wont lock:

a. VCC to PLL not stable - need to capture scope shot

b. unstable refclk - need to capture scopeshot

c. PLL reset signal triggered - need to check schematic


regards,

Farabi



  • Elad0708's avatar
    Elad0708
    Icon for New Contributor rankNew Contributor
    1 year ago

    Hi Farabi,

    Thank you for your response. The model I have issue is simulation and not lab test.

    In simulation the pll doesn't lock or drive any clock at his outputs.

    Regards,

    Elad