Forum Discussion
Elad0708
New Contributor
New ContributorDpX4 Simulation
I Created design based on DPX4 5.4GHz. The example design includes 'dp_gxb_sysclk' module. According to Ip generation the reference clock supposed to be 150Mhz. I created simulation based on this des...
Farabi_Altera
Regular Contributor
Regular ContributorHello,
We will look into your PLL setting first.
- Do you have design example we can check your PLL parameters?
- If you reduce the output clock speed- can it lock?
possible cause PLL wont lock:
a. VCC to PLL not stable - need to capture scope shot
b. unstable refclk - need to capture scopeshot
c. PLL reset signal triggered - need to check schematic
regards,
Farabi
Elad0708New Contributor
New ContributorHi Farabi,
Thank you for your response. The model I have issue is simulation and not lab test.
In simulation the pll doesn't lock or drive any clock at his outputs.
Regards,
Elad
