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Elad0708's avatar
Elad0708
Icon for New Contributor rankNew Contributor
2 years ago

DpX4 Simulation

I Created design based on DPX4 5.4GHz. The example design includes 'dp_gxb_sysclk' module. According to Ip generation the reference clock supposed to be 150Mhz. I created simulation based on this des...
Fpga Devkit
VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi Elad,


Are you following the steps outlined in Section 1.3 of the User Guide below to generate the Design Example for the DisplayPort Intel FPGA IP?


Please note that in this release, simulation is not yet supported for Agilex™ 7 F-Tile devices.


F-Tile DisplayPort Intel® FPGA IP Design Example User Guide


Thanks.

Best Regards,

Ven