SKGR0
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New ContributorDDR4 Memory Access with Tartget Device - Arria10
I have generated altera_emif IP with the following parameters:
- Protocol : DDR4
- Target Device: Arria10
- Memory Clock frequency : 1200 MHz
- Clock Rate of user logic: Quarter
- User logic clock: 300 MHz
- DQ Width : 32 bits
- amm_readdata and amm_writedata : 256 bits
The above configuration summarizes to the following statements:
- FPGA Receives 64 bits at from DDR4 at 1200 MHz at every clock (32 bits in positive edge and 32 bits in negative edge)
- Avalon interface works at 300 MHz (quarter rate)
- Avalon interface sends out 256 bits data (32*8) at 300 MHz at every clock.
- Bandwidth = 1200 * 1000000 (MHz) * 2 * 32 / (10^9) = 76.8 Giga bits per second.
Is my understanding correct?Please Confirm.
Hi,
Your understanding on all questions 1 to 4 are correct.
One thing to take note is whatever bandwidth calculation that we discussed so far is "theoretical max bandwidth"
Actual data transfer throughput may vary depending on following factor
- Whether user design application is able to process and transfer data on every clock cycle or is user executing sequence or random SDRAM address accessing
- It's impossible for DDR4 IP controller to process data transfer every clock cycle. DDR4 IP will gate avalon_ready signal if it's busy and unable to accept data transfer
- It's impossible for DDR4 SDRAM to accept data transfer every clock cycle due to internal write/read timing switch requirement and also SDRAM refresh cycle requirement
Thanks.
Regards,
dlim
