Forum Discussion
SKGR0
New Contributor
New ContributorDDR4 Memory Access with Tartget Device - Arria10
I have generated altera_emif IP with the following parameters: Protocol : DDR4 Target Device: Arria10 Memory Clock frequency : 1200 MHz Clock Rate of user logic: Quarter User logic clock: 300 M...
Hi,
Your understanding on all questions 1 to 4 are correct.
One thing to take note is whatever bandwidth calculation that we discussed so far is "theoretical max bandwidth"
Actual data transfer throughput may vary depending on following factor
- Whether user design application is able to process and transfer data on every clock cycle or is user executing sequence or random SDRAM address accessing
- It's impossible for DDR4 IP controller to process data transfer every clock cycle. DDR4 IP will gate avalon_ready signal if it's busy and unable to accept data transfer
- It's impossible for DDR4 SDRAM to accept data transfer every clock cycle due to internal write/read timing switch requirement and also SDRAM refresh cycle requirement
Thanks.
Regards,
dlim
Deshi_Intel
Regular Contributor
Regular ContributorHi,
Your understanding on all questions 1 to 4 are correct.
One thing to take note is whatever bandwidth calculation that we discussed so far is "theoretical max bandwidth"
Actual data transfer throughput may vary depending on following factor
- Whether user design application is able to process and transfer data on every clock cycle or is user executing sequence or random SDRAM address accessing
- It's impossible for DDR4 IP controller to process data transfer every clock cycle. DDR4 IP will gate avalon_ready signal if it's busy and unable to accept data transfer
- It's impossible for DDR4 SDRAM to accept data transfer every clock cycle due to internal write/read timing switch requirement and also SDRAM refresh cycle requirement
Thanks.
Regards,
dlim
SKGR0New Contributor
New ContributorThanks!!
In addition to the above query,
I observed that DDR4 limits the burst length to 8 (BL8)
Does this mean , if DQ Width is 32 , with one DDR read request I would be able to receive maximum of 256 bits (32 *8) ?
