DDR4 Memory Access with Tartget Device - Arria10

Hi,

Your understanding on all questions 1 to 4 are correct.

One thing to take note is whatever bandwidth calculation that we discussed so far is "theoretical max bandwidth"

Actual data transfer throughput may vary depending on following factor

1. Whether user design application is able to process and transfer data on every clock cycle or is user executing sequence or random SDRAM address accessing
2. It's impossible for DDR4 IP controller to process data transfer every clock cycle. DDR4 IP will gate avalon_ready signal if it's busy and unable to accept data transfer
3. It's impossible for DDR4 SDRAM to accept data transfer every clock cycle due to internal write/read timing switch requirement and also SDRAM refresh cycle requirement

Thanks.

Regards,

dlim