Forum Discussion
New ContributorDDR4 Memory Access with Tartget Device - Arria10
Hi,
Your understanding on all questions 1 to 4 are correct.
One thing to take note is whatever bandwidth calculation that we discussed so far is "theoretical max bandwidth"
Actual data transfer throughput may vary depending on following factor
- Whether user design application is able to process and transfer data on every clock cycle or is user executing sequence or random SDRAM address accessing
- It's impossible for DDR4 IP controller to process data transfer every clock cycle. DDR4 IP will gate avalon_ready signal if it's busy and unable to accept data transfer
- It's impossible for DDR4 SDRAM to accept data transfer every clock cycle due to internal write/read timing switch requirement and also SDRAM refresh cycle requirement
Thanks.
Regards,
dlim
Regular ContributorHI,
There are 2 sides of data transaction flow as below.
- User logic <=> DDR4 IP <=> DDR4 SDRAM
BL8 is applicable for the data transaction between DDR4 IP <=> DDR4 SDRAM which is defined by JEDEC spec.
I believed the higher burstcount is happening on example design data flow between User logic <=> DDR4 IP, right ?
User can blast a lot of data to DDR4 IP but it will be queue and process accordingly inside the DDR4 IP to be transferred to DDR4 SDRAM later with BL8.
I hope I clear your doubt. Thanks.
Regards,
dlim
New ContributorHi
Thanks , it is clear now.
Further calculating the DDR4 latency.
Time taken between raising the read request and retrieving the the first word from Memory is
Latency = CAS Latency/ Memory clock speed * (2000) nanoseconds
example: for DDR4 - 2400, Clock speed - 1200MHz , if CL = 15
Latency = (1200/15)*2000 = 25 nanoseconds
My question is :
If I request a burst count of 32 (4 *BL8) , What would be the total latency to receive the data ?
Is it , 4 (BL8) Read requests * 25 = 100 nanoseconds ?
Or , 1 Read request * 25 = 25 nanoseconds?
Thanks in advance!
