Forum Discussion
New ContributorDDR4 Memory Access with Tartget Device - Arria10
Hi,
Your understanding on all questions 1 to 4 are correct.
One thing to take note is whatever bandwidth calculation that we discussed so far is "theoretical max bandwidth"
Actual data transfer throughput may vary depending on following factor
- Whether user design application is able to process and transfer data on every clock cycle or is user executing sequence or random SDRAM address accessing
- It's impossible for DDR4 IP controller to process data transfer every clock cycle. DDR4 IP will gate avalon_ready signal if it's busy and unable to accept data transfer
- It's impossible for DDR4 SDRAM to accept data transfer every clock cycle due to internal write/read timing switch requirement and also SDRAM refresh cycle requirement
Thanks.
Regards,
dlim
Regular ContributorHI,
Sorry, Intel FPGA doesn't have DMA linux driver example as we are just DDR4 IP memory controller solution provider rather than system level application solution provider.
For your enquiry on burst length of 8,
- Yes, one read request on burst length of 8 will transfer total of 256 bit data (32 x 8)
- But do take note this whole process happen over 4 clock cycle, each clock cycle transfer 2 times of data (rising edge + falling edge)
- Each burst only transfer 32 bits of data where 256 bits data transfer is achieved via 8 times of data transfer using only one read command
Thanks.
Regards,
dlim
SKGR0Previous query :
I observed that DDR4 limits the burst length to 8 (BL8)
Does this mean , if DQ Width is 32 , with one DDR read request I would be able to receive maximum of 256 bits (32 *8) ?
Further on enquiry on burst length of 8
I tried instantiating a DDR4 Controller IP for Arria 10 device and simulated the example design.
I found that amm_burstcount = 58 in the example design.
And this contradicts with the statement that the DDR4 IP constraints the burst length to 8 (Fixed BL8).
Can someone please clarify on this?
Thanks in advance!
