Data from FPGA to host

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I think I don't have to use a Nios cpu. I prefer to use a system like the one in your de0_nano_sdram tutorial. Only I have to add PIOs to read from/write to my fifo in the Quartus top-level. I just have to add commands in the jtag_cmds.tcl script to access these PIOs. Is it possible the way you wrote it?

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That will depends on what the PIOs are doing. If they are static, then sure you can just read them. In your earlier posts, you commented you wanted to read toggling signals. In that case, you really need to capture them first, eg., into on-chip RAM, or into SDRAM, and then read them out via JTAG. This is pretty much what SignalTap II does (with the samples stored in on-chip RAM). If you cannot figure out how to trigger SignalTap II correctly, then you'll probably having trouble getting this scheme to work too.

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For the simulation, I think (after wondering and having problems without that) it's really important. I PROMISE I will learn how to do it but I don't find a good tutorial for that. I've found Simulating Designs with Lower-Level Qsys Systems or AN351 but it's with a Nios II and I'd like a simpler tutorial with a simpler Qsys system but I don't find any for now. Do you know any? Or maybe you even wrote one.

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I gave you a link to a tutorial back in Post#35.

Cheers,

Dave

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That will depends on what the PIOs are doing. If they are static, then sure you can just read them. In your earlier posts, you commented you wanted to read toggling signals. In that case, you really need to capture them first, eg., into on-chip RAM, or into SDRAM, and then read them out via JTAG. This is pretty much what SignalTap II does (with the samples stored in on-chip RAM). If you cannot figure out how to trigger SignalTap II correctly, then you'll probably having trouble getting this scheme to work too.

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I'm not English so I think I miss some subtlety in the words and I'm not sure I understand it correctly: the signals are coming from a fifo. Is it correct to say they're static? Or how can I manage it?

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I gave you a link to a tutorial back in Post#35.

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I should have read it too quickly, I'll read it again and more carefully...

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I'm not English so I think I miss some subtlety in the words and I'm not sure I understand it correctly: the signals are coming from a fifo. Is it correct to say they're static? Or how can I manage it?

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Static = signals are not changing.

Dynamic = signals are changing.

In your case, the signals are dynamic, so you really need to design a data capture system. If you can figure out how to *simulate* a design where you capture data into RAM or SDRAM, then you can use that.

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I should have read it too quickly, I'll read it again and more carefully...

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Yes. At least you will see how to simulate a Qsys system.

In your case though, you need to start off simpler and simulate the external signals you are trying to capture, and the logic needed to capture them.

Of course, this is already implemented by SignalTap II, so perhaps you should spend a little more time understanding how to use that ...

Cheers,

Dave

But the signals are changing depending on ext_clk that is about 100 times slower than the original clock and these signals are resynchronized by a fifo between the Quartus design and the Qsys system. It's not enough to say they are static?

And a "no matter" question: what is (is there) the command I have to use in Quartus to list the content of the working directory? I tried 'ls' and 'dir' but it won't work.

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But the signals are changing depending on ext_clk that is about 100 times slower than the original clock and these signals are resynchronized by a fifo between the Quartus design and the Qsys system. It's not enough to say they are static?

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If you are reading the data via the USB JTAG interface then, the read interface is the limiting factor. So your signals are dynamic, and need to be captured into RAM, and then that RAM can be read out over USB.

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And a "no matter" question: what is (is there) the command I have to use in Quartus to list the content of the working directory? I tried 'ls' and 'dir' but it won't work.

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The Quartus console is a Tcl console, you can use Tcl commands.

Cheers,

Dave

I'm doing your altera_jtag_to_avalon_mm_tutorial but I got errors.

When doing 4.5.2 I first have multiple warnings when running "com":

** Warning: ./..//submodules/altera_merlin_traffic_limiter.sv(512): (vlog-2583)  - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.

Then I get errors when running "vlog -sv $TUTORIAL/hdl/qsys_system/test/qsys_system_bfm_master_tb.sv

-L qsys_system_bfm_master":

** Error: C:/Users/rm231795/Documents/work/JTAG/cellule/quartus/jtag_to_avalon_mm_tutorial/hdl/qsys_system/test/qsys_system_bfm_master_tb.sv(48): Could not find the package (verbosity_pkg).  Design read will continue, but expect a cascade of errors after this failure.  Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line.

And when trying 4.5.3 I get

# vsim +nowarnTFMPC -L work -L work_lib -L altera_common_sv_packages -L rsp_xbar_mux -L rsp_xbar_demux -L cmd_xbar_mux -L cmd_xbar_demux -L limiter -L id_router -L addr_router -L led_pio_s1_translator_avalon_universal_slave_0_agent -L bfm_master_m0_translator_avalon_universal_master_0_agent -L led_pio_s1_translator -L bfm_master_m0_translator -L p2b_adapter -L b2p_adapter -L transacto -L p2b -L b2p -L fifo -L timing_adt -L jtag_phy_embedded_in_jtag_master -L rst_controller -L mm_interconnect_0 -L onchip_ram -L button_pio -L led_pio -L jtag_master -L bfm_master -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -t ps qsys_system_jtag_master_tb #  ** Error: Failure to obtain a Verilog simulation license. Unable to checkout any of these license features: alteramtivsim or alteramtivlog.#  Error loading design

when trying "elab +nowarnTFMPC"

I see license problems. I think it's because I'm using only VHDL and not VERILOG at work so I changed Qsys choices to generate VHDL but I have other errors.

What can I do?

------------ add -------------------

I thought of a license problem so I used the ASE version (no license required) but it's the same: first warnings, then errors...

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I changed Qsys choices to generate VHDL

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You can only do that if you have a full license of Modelsim-SE, otherwise you have to simulate with a single language.

The other error is discussed in the thread related to the tutorial;

http://www.alteraforum.com/forum/showthread.php?t=34787

Cheers,

Dave

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You can only do that if you have a full license of Modelsim-SE, otherwise you have to simulate with a single language.

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I think I have but I'm trying with verilog...

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The other error is discussed in the thread related to the tutorial;

http://www.alteraforum.com/forum/showthread.php?t=34787

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Can you tell me which post because there are so many !

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Can you tell me which post because there are so many !

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Sorry, its post# 52, but that actually points to the discussion in this thread:

http://www.alteraforum.com/forum/showthread.php?t=34787

Read the readme.txt in the zip file in Post#25.

Cheers,

Dave

I read your readme.txt.Here is what I've done:

- modelsim ASE 10.1.d

- set TUTORIAL

- cd $TUTORIAL/qsys/qsys_system/simulation/mentor

- source msim_setup.tcl

- dev_com

- com -> some warnings

- vlog -sv $TUTORIAL/hdl/qsys_system/test/qsys_system_bfm_master_tb.sv -L altera_common_sv_packages

- set TOP_LEVEL_NAME qsys_system_bfm_master_tb

- elab +nowarnTFMPC ->

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elab +nowarnTFMPC

# [exec] elab

# vsim +nowarnTFMPC -L work -L work_lib -L altera_common_sv_packages -L rsp_xbar_mux -L rsp_xbar_demux -L cmd_xbar_mux -L cmd_xbar_demux -L limiter -L id_router -L addr_router -L led_pio_s1_translator_avalon_universal_slave_0_agent -L bfm_master_m0_translator_avalon_universal_master_0_agent -L led_pio_s1_translator -L bfm_master_m0_translator -L p2b_adapter -L b2p_adapter -L transacto -L p2b -L b2p -L fifo -L timing_adt -L jtag_phy_embedded_in_jtag_master -L rst_controller -L mm_interconnect_0 -L onchip_ram -L button_pio -L led_pio -L jtag_master -L bfm_master -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -t ps qsys_system_bfm_master_tb

# Loading sv_std.std

# Loading altera_common_sv_packages.verbosity_pkg

# Loading altera_common_sv_packages.avalon_mm_pkg

# Loading work.qsys_system_bfm_master_tb

# Loading work.qsys_system

# Loading altera_common_sv_packages.avalon_utilities_pkg

# Loading bfm_master.altera_avalon_mm_master_bfm

# Loading jtag_master.qsys_system_jtag_master

# Loading jtag_phy_embedded_in_jtag_master.altera_avalon_st_jtag_interface

# Loading timing_adt.qsys_system_jtag_master_timing_adt

# Loading limiter.altera_avalon_sc_fifo

# Loading b2p.altera_avalon_st_bytes_to_packets

# Loading p2b.altera_avalon_st_packets_to_bytes

# Loading transacto.altera_avalon_packets_to_master

# Loading b2p_adapter.qsys_system_jtag_master_b2p_adapter

# Loading p2b_adapter.qsys_system_jtag_master_p2b_adapter

# Loading rst_controller.altera_reset_controller

# Loading led_pio.qsys_system_led_pio

# Loading button_pio.qsys_system_button_pio

# Loading onchip_ram.qsys_system_onchip_ram

# ** Error: (vsim-42) Unsupported ModelSim library format for "C:/Users/rm231795/Documents/work/JTAG/cellule/quartus/jtag_to_avalon_mm_tutorial/qsys/qsys_system/simulation/mentor/libraries/altera_ver". (Format: 4)

.

.

.

# Error loading design

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I can't post everything because of length limitation.

The first error is a library type and I don't know what to do.