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Altera_Forum's avatar
Altera_Forum
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11 years ago

Data from FPGA to host

Hi, I have a DE0-nano board and I compute data (only 4 bits generated at about 10MHz) and I'd like to communicate it to the host cpu through the USB-blaster so programs could read it. I've read th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

But the signals are changing depending on ext_clk that is about 100 times slower than the original clock and these signals are resynchronized by a fifo between the Quartus design and the Qsys system. It's not enough to say they are static?

And a "no matter" question: what is (is there) the command I have to use in Quartus to list the content of the working directory? I tried 'ls' and 'dir' but it won't work.