Honored Contributor
Honored ContributorI'm doing your altera_jtag_to_avalon_mm_tutorial but I got errors.
When doing 4.5.2 I first have multiple warnings when running "com":** Warning: ./..//submodules/altera_merlin_traffic_limiter.sv(512): (vlog-2583) - Some checking for conflicts with always_comb and always_latch variables not yet supported. Run vopt to provide additional design-level checks.** Error: C:/Users/rm231795/Documents/work/JTAG/cellule/quartus/jtag_to_avalon_mm_tutorial/hdl/qsys_system/test/qsys_system_bfm_master_tb.sv(48): Could not find the package (verbosity_pkg). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line.# vsim +nowarnTFMPC -L work -L work_lib -L altera_common_sv_packages -L rsp_xbar_mux -L rsp_xbar_demux -L cmd_xbar_mux -L cmd_xbar_demux -L limiter -L id_router -L addr_router -L led_pio_s1_translator_avalon_universal_slave_0_agent -L bfm_master_m0_translator_avalon_universal_master_0_agent -L led_pio_s1_translator -L bfm_master_m0_translator -L p2b_adapter -L b2p_adapter -L transacto -L p2b -L b2p -L fifo -L timing_adt -L jtag_phy_embedded_in_jtag_master -L rst_controller -L mm_interconnect_0 -L onchip_ram -L button_pio -L led_pio -L jtag_master -L bfm_master -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -t ps qsys_system_jtag_master_tb # ** Error: Failure to obtain a Verilog simulation license. Unable to checkout any of these license features: alteramtivsim or alteramtivlog.# Error loading design
