Data from FPGA to host

I read your readme.txt.Here is what I've done:

- modelsim ASE 10.1.d

- set TUTORIAL

- cd $TUTORIAL/qsys/qsys_system/simulation/mentor

- source msim_setup.tcl

- dev_com

- com -> some warnings

- vlog -sv $TUTORIAL/hdl/qsys_system/test/qsys_system_bfm_master_tb.sv -L altera_common_sv_packages

- set TOP_LEVEL_NAME qsys_system_bfm_master_tb

- elab +nowarnTFMPC ->

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elab +nowarnTFMPC

# [exec] elab

# vsim +nowarnTFMPC -L work -L work_lib -L altera_common_sv_packages -L rsp_xbar_mux -L rsp_xbar_demux -L cmd_xbar_mux -L cmd_xbar_demux -L limiter -L id_router -L addr_router -L led_pio_s1_translator_avalon_universal_slave_0_agent -L bfm_master_m0_translator_avalon_universal_master_0_agent -L led_pio_s1_translator -L bfm_master_m0_translator -L p2b_adapter -L b2p_adapter -L transacto -L p2b -L b2p -L fifo -L timing_adt -L jtag_phy_embedded_in_jtag_master -L rst_controller -L mm_interconnect_0 -L onchip_ram -L button_pio -L led_pio -L jtag_master -L bfm_master -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -t ps qsys_system_bfm_master_tb

# Loading sv_std.std

# Loading altera_common_sv_packages.verbosity_pkg

# Loading altera_common_sv_packages.avalon_mm_pkg

# Loading work.qsys_system_bfm_master_tb

# Loading work.qsys_system

# Loading altera_common_sv_packages.avalon_utilities_pkg

# Loading bfm_master.altera_avalon_mm_master_bfm

# Loading jtag_master.qsys_system_jtag_master

# Loading jtag_phy_embedded_in_jtag_master.altera_avalon_st_jtag_interface

# Loading timing_adt.qsys_system_jtag_master_timing_adt

# Loading limiter.altera_avalon_sc_fifo

# Loading b2p.altera_avalon_st_bytes_to_packets

# Loading p2b.altera_avalon_st_packets_to_bytes

# Loading transacto.altera_avalon_packets_to_master

# Loading b2p_adapter.qsys_system_jtag_master_b2p_adapter

# Loading p2b_adapter.qsys_system_jtag_master_p2b_adapter

# Loading rst_controller.altera_reset_controller

# Loading led_pio.qsys_system_led_pio

# Loading button_pio.qsys_system_button_pio

# Loading onchip_ram.qsys_system_onchip_ram

# ** Error: (vsim-42) Unsupported ModelSim library format for "C:/Users/rm231795/Documents/work/JTAG/cellule/quartus/jtag_to_avalon_mm_tutorial/qsys/qsys_system/simulation/mentor/libraries/altera_ver". (Format: 4)

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# Error loading design

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I can't post everything because of length limitation.

The first error is a library type and I don't know what to do.