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I think I don't have to use a Nios cpu. I prefer to use a system like the one in your de0_nano_sdram tutorial. Only I have to add PIOs to read from/write to my fifo in the Quartus top-level. I just have to add commands in the jtag_cmds.tcl script to access these PIOs. Is it possible the way you wrote it?
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That will depends on what the PIOs are doing. If they are static, then sure you can just read them. In your earlier posts, you commented you wanted to read toggling signals. In that case, you really need to capture them first, eg., into on-chip RAM, or into SDRAM, and then read them out via JTAG. This is pretty much what SignalTap II does (with the samples stored in on-chip RAM). If you cannot figure out how to trigger SignalTap II correctly, then you'll probably having trouble getting this scheme to work too.
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For the simulation, I think (after wondering and having problems without that) it's really important. I PROMISE I will learn how to do it but I don't find a good tutorial for that. I've found Simulating Designs with Lower-Level Qsys Systems or AN351 but it's with a Nios II and I'd like a simpler tutorial with a simpler Qsys system but I don't find any for now. Do you know any? Or maybe you even wrote one.
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I gave you a link to a tutorial back in Post#35.
Cheers,
Dave
Honored Contributor
