Forum Discussion
Altera_Forum
Honored Contributor
11 years agoData from FPGA to host
Hi, I have a DE0-nano board and I compute data (only 4 bits generated at about 10MHz) and I'd like to communicate it to the host cpu through the USB-blaster so programs could read it. I've read th...
Altera_Forum
Honored Contributor
11 years ago --- Quote Start --- I'm not English so I think I miss some subtlety in the words and I'm not sure I understand it correctly: the signals are coming from a fifo. Is it correct to say they're static? Or how can I manage it? --- Quote End --- Static = signals are not changing. Dynamic = signals are changing. In your case, the signals are dynamic, so you really need to design a data capture system. If you can figure out how to *simulate* a design where you capture data into RAM or SDRAM, then you can use that. --- Quote Start --- I should have read it too quickly, I'll read it again and more carefully... --- Quote End --- Yes. At least you will see how to simulate a Qsys system. In your case though, you need to start off simpler and simulate the external signals you are trying to capture, and the logic needed to capture them. Of course, this is already implemented by SignalTap II, so perhaps you should spend a little more time understanding how to use that ... Cheers, Dave