New ContributorCyclone V - CLK[0:11][P:N] Connection
Hi,
In our schematics we have some of the CLK[0:11]P pins used as single-ended input clocks and related CLK[0:11]N pins connected with 5K pull-down resistor to GND.
I saw in the Cyclone V documentation:
1. In Cyclone V documentation Intel recommend to tie the CLK[0:11]N pins to GND or leave them unconnected and configure them as internally bias in Quartus.
2. In Cyclone V EVK schematics Intel tied the CLK[0:11]N pins to GND.
Please your support understanding what is the impact of connecting the CLK[0:11]N pins with 5K pull-down resistor to GND instead of tied to GND?
Thanks,
Roy Roif
Hi,
"Please your support understanding what is the impact of connecting the CLK[0:11]N pins with 5K pull-down resistor to GND instead of tied to GND?"
I don't see 5k pull-down for unused clock input suggested in an Intel document, and I don't see a specific advantage or "impact".
Cyclone V is providing weak pull-up and other options to bias unconnected input pins, different from other FPGA families, the option is also available for clock pins. We see grounded unused clock pins with other FPGA families that don't have this bias option for clock pins.
Pull-down resistors are partly suggested for unused refclock inputs of gigabit transceivers. These pins use different I/O standards and have therefore different requirements. It makes no sense to copy the suggestion for standard clock inputs.
