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royroif's avatar
royroif
Icon for New Contributor rankNew Contributor
2 years ago
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Cyclone V - CLK[0:11][P:N] Connection

Hi, In our schematics we have some of the CLK[0:11]P pins used as single-ended input clocks and related CLK[0:11]N pins connected with 5K pull-down resistor to GND. I saw in the Cyclone V documenta...
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  • FvM's avatar
    FvM
    2 years ago

    Hi,

    "Please your support understanding what is the impact of connecting the CLK[0:11]N pins with 5K pull-down resistor to GND instead of tied to GND?"

    I don't see 5k pull-down for unused clock input suggested in an Intel document, and I don't see a specific advantage or "impact".

    Cyclone V is providing weak pull-up and other options to bias unconnected input pins, different from other FPGA families, the option is also available for clock pins. We see grounded unused clock pins with other FPGA families that don't have this bias option for clock pins.

    Pull-down resistors are partly suggested for unused refclock inputs of gigabit transceivers. These pins use different I/O standards and have therefore different requirements. It makes no sense to copy the suggestion for standard clock inputs.

AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hello Roy,


It can be both, depending on your design.


"When you use the single-ended I/O standard, only the CLK[0:11]p pins serve as the dedicated input."

"When you do not use these pins, Altera recommends tying them to GND or leaving them unconnected. If these pins are unconnected, use the Quartus Prime software programmable options to internally bias these pins."


You can refer to the Pin Connection Guidelines for the pin named "CCLK[0:11][p:n]" on page 2 from Cyclone® V GX, GT, E, SX, ST and SE Device Family Pin Connection Guidelines documentation. Refer to below link:


https://www.intel.com/content/www/us/en/content-details/654351/cyclone-v-gx-gt-e-sx-st-and-se-device-family-pin-connection-guidelines.html


Regards,

Aqid