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Altera_Forum's avatar
Altera_Forum
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15 years ago

Cyclone III Starter kit--DDR SDRAM address mapping (NIOS II)

Dear all, I did a DDR SDRAM memory test on Cyclone III Starter Kit, I changed the 'hello_world0" program.

When I write '0' to address '0', read the data out at address'0', the result is '0', correct ;

But when I write '1' to address '1', read the data out again at address'0', the result at address'0' is not '0' anymore, but change to '1'!

It seems the writing at address '1' affects the data on address'0'.

My question is: Is address'0' and address'1' the same address for writing SDRAM?

The DDR SDRAM is only 13 bit address, but the SOPC SDRAM controller altmemddr has 26 bit address (0x02000000-0x03ffffff), how the 13 bit address is mapping to 26 bit address to connect to Avalon switch fabric?

The program and running result is in the following:

# include <stdio.h># include "system.h"# include "io.h"# include "altera_avalon_pio_regs.h"

int main()

{

int i;

int error_count;

int readbyte;

error_count = 0;

i=0;

IOWR_16DIRECT(ALTMEMDDR_BASE, i, i);

printf("i is %d\n",i);

i = 0;

readbyte = IORD_16DIRECT(ALTMEMDDR_BASE, i);

printf("readbyte is %d\n",readbyte);

i=1;

IOWR_16DIRECT(ALTMEMDDR_BASE, i, i);

printf("i is %d\n",i);

i = 0;

readbyte = IORD_16DIRECT(ALTMEMDDR_BASE, i);

printf("readbyte is %d\n",readbyte);

return error_count;

}

Nios II console output:

i is 0

readybyte is 0

i is 1

readbyte is 1

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    The DDR SDRAM is only 13 bit address, but the SOPC SDRAM controller altmemddr has 26 bit address (0x02000000-0x03ffffff), how the 13 bit address is mapping to 26 bit address to connect to Avalon switch fabric?

    --- Quote End ---

    The SDRAM on the Cyclone III Starter kit is 256 Mbit = 32 MByte. To address 32 MByte as bytes, you need 25 bits.

    0x02000000-0x03ffffff is a range of 0x01ffffff which is actually 25 bits.

    The reason there are only 13 address lines is the because the addressing of SDRAM is actually split up into a matrix of row address and column address with multiple banks. The row address and column address are sent at separate times over the same address lines.

    The memory on the starter kit uses 13 row address bits, 9 column address bits and 2 bank address bits for a total of 24 bits. The output is 16 bits wide. 2^24 * 16 = 256Mbit.

    None of this actually solves your problem, but it should help you understand a bit more how the system should work.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thank you, Kevin, it did explain sth.

    So how the total 24 bits of row/column/bank address maps to 25 bits of the SOPC SDRAM controller altmemddr address ? Is this extra bit MSB or LSB?

    If it is LSB, then it can explain my program.

    The control panel of Cyclone III Strater kit do use 24 bits address in the user interface to control DDR SDRAM. But it didn't use SOPC in the Quartus II project.

    By the way, I can only find 13 address bits and 2 bank address bits and 1 column address bit, 1 row address bit on the schematics, but can not find total 9 column address bits as you said. Could you?

    Thanks!

    --- Quote Start ---

    The SDRAM on the Cyclone III Starter kit is 256 Mbit = 32 MByte. To address 32 MByte as bytes, you need 25 bits.

    0x02000000-0x03ffffff is a range of 0x01ffffff which is actually 25 bits.

    The reason there are only 13 address lines is the because the addressing of SDRAM is actually split up into a matrix of row address and column address with multiple banks. The row address and column address are sent at separate times over the same address lines.

    The memory on the starter kit uses 13 row address bits, 9 column address bits and 2 bank address bits for a total of 24 bits. The output is 16 bits wide. 2^24 * 16 = 256Mbit.

    None of this actually solves your problem, but it should help you understand a bit more how the system should work.

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    So how the total 24 bits of row/column/bank address maps to 25 bits of the SOPC SDRAM controller altmemddr address ? Is this extra bit MSB or LSB?

    --- Quote End ---

    The 24 bit address is a word address. The word size of the memory is 16 bit. The 25 bit address in SOPC builder is a byte address.

    Even though the memory uses a word address, it is still possible to write a single byte using the data mask pins (LDM and UDM).

    --- Quote Start ---

    By the way, I can only find 13 address bits and 2 bank address bits and 1 column address bit, 1 row address bit on the schematics, but can not find total 9 column address bits as you said.

    --- Quote End ---

    The row address and column address are both written using the same address pins. The RAS (row address select) and CAS (column address select) signals are used to indicate which part of the address is currently being written to the SDRAM.