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So how the total 24 bits of row/column/bank address maps to 25 bits of the SOPC SDRAM controller altmemddr address ? Is this extra bit MSB or LSB?
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The 24 bit address is a word address. The word size of the memory is 16 bit. The 25 bit address in SOPC builder is a byte address.
Even though the memory uses a word address, it is still possible to write a single byte using the data mask pins (LDM and UDM).
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By the way, I can only find 13 address bits and 2 bank address bits and 1 column address bit, 1 row address bit on the schematics, but can not find total 9 column address bits as you said.
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The row address and column address are both written using the same address pins. The RAS (row address select) and CAS (column address select) signals are used to indicate which part of the address is currently being written to the SDRAM.
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