Cyclone III Starter kit--DDR SDRAM address mapping (NIOS II)

Thank you, Kevin, it did explain sth.

So how the total 24 bits of row/column/bank address maps to 25 bits of the SOPC SDRAM controller altmemddr address ? Is this extra bit MSB or LSB?

If it is LSB, then it can explain my program.

The control panel of Cyclone III Strater kit do use 24 bits address in the user interface to control DDR SDRAM. But it didn't use SOPC in the Quartus II project.

By the way, I can only find 13 address bits and 2 bank address bits and 1 column address bit, 1 row address bit on the schematics, but can not find total 9 column address bits as you said. Could you?

Thanks!

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The SDRAM on the Cyclone III Starter kit is 256 Mbit = 32 MByte. To address 32 MByte as bytes, you need 25 bits.

0x02000000-0x03ffffff is a range of 0x01ffffff which is actually 25 bits.

The reason there are only 13 address lines is the because the addressing of SDRAM is actually split up into a matrix of row address and column address with multiple banks. The row address and column address are sent at separate times over the same address lines.

The memory on the starter kit uses 13 row address bits, 9 column address bits and 2 bank address bits for a total of 24 bits. The output is 16 bits wide. 2^24 * 16 = 256Mbit.

None of this actually solves your problem, but it should help you understand a bit more how the system should work.

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