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Altera_Forum
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17 years agoCyclone III / Bitec Video Dev Kit
Hi
I got the Cyclone III dev kit a few days ago together with the Bitec dvi in/out and the quad comp board. First I tried to run the 71 vesion of Quartus II and Nios II on Vista ...no luck I then downloaded the ver 81 of both and still had problems on Vista then I installed on Xp and it seems to work :-) I can do the Counter demo in QuartusII, great I can do the Hello World in Nios II, great Then I try to do the Moasic for 4xcomp with the Bitec code and I can build all. But when I do right click on "hsmc_quad_video_demo and select run as Niro II hardware it do build a bit more and try to download with this result Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Pausing target processor: OK Initializing CPU cache (if present) OK Downloading 00000000 ( 0%) Downloaded 9KB in 0.1s Verifying 00000000 ( 0%) Verify failed between address 0x0 and 0x200F Leaving target processor paused I would be very happy if someone have a good hint to get pass this point Thank you Wiljan11 Replies
- Altera_Forum
Honored Contributor
It's good known issue with a very wide possible reasons. Usually it happens due to memory or download cable error. Check that you get USB Cable Rev.C and that you code and data areas assigned properly.
- Altera_Forum
Honored Contributor
Hi
After a lot of different test I now have sample to work :) The real promlem was that I had to dowload the sof file before I right clik and say run as NIOS hardware ... then the verify error are gone... so far so good Now to what I really want to achieve I want to be able to run the Clyclone III with the Bitec DVI in / out for 1024x768@60 or higher The input video should be scaled down in size to like 25% and the been shown on the output DVI as 3 small windows (the rest are black) The window at the left should be rotated 90 deg CCW and the window to the right should be rotatec 90 deg CW and the one in the top should not be rotated Can someone recommend the best way to have this to work from some of the sample avaible? Or if you have other sugestions http://www.tech2net.dk/media/input.jpg http://www.tech2net.dk/media/output.jpg Best regards Wiljan - Altera_Forum
Honored Contributor
Hi
A bit more progress To better understand how stuff works I have done the following On a XP installation I have Nios 8.1 and Quartus II 8.1 from http://www.bitec.ltd.uk/ciii_video_dev_kit.html I have taken the Quad demo http://www.bitec.ltd.uk/outgoing/bitec_hsmc_quad_video_28mar08.zip This demo do genererate a VGA out 640x480 and you can input 4 composite video which will be scaled and you can see up to 4 live input at the output like a quad split First I do copy all the files from the demo to C:/altera/Bitec/bitec_hsmc_quad_video I now follow the instrucrion in the pdf file Now it all works fine as described in the doc I have managed to mod a bit on the position of the input to the frame buffer and if I connect the 3 input in parrallel with some wire I do see the same video in 3 windows on the output http://www.tech2net.dk/media/still_01.jpg So instead of having the wire parrallel I now mowe to Quartus II and select open exsisting project and browse to C:\altera\bitec\bitec_hsmc_quad_video\QuartusII_7.2\hsmc_qvideo_C120_dev_kit_mosaic_dvi.qpf file and open it Before I try to modify anything I do a start compilation and after long time I do have some errors like Info: Type bi-directional pin membot_dq[18] uses the SSTL-18 Class I I/O standard Info: Type bi-directional pin membot_dq[2] uses the SSTL-18 Class I I/O standard Info: Following pins have the same output enable: nios2:inst|i2c:the_i2c|oc_i2c_master:the_oc_i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1|i2c_master_bit_ctrl:u1|iscl_oen (inverted) Info: Type bi-directional pin SCL uses the 2.5 V I/O standard Info: Following pins have the same output enable: nios2:inst|i2c:the_i2c|oc_i2c_master:the_oc_i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1|i2c_master_bit_ctrl:u1|isda_oen (inverted) Info: Type bi-directional pin SDA uses the 2.5 V I/O standard Error: Quartus II Fitter was unsuccessful. 2 errors, 22 warnings Error: Peak virtual memory: 331 megabytes Error: Processing ended: Sat Jan 24 17:47:37 2009 Error: Elapsed time: 00:00:16 Error: Total CPU time (on all processors): 00:00:15 Error: Quartus II Full Compilation was unsuccessful. 4 errors, 15 warnings So now I would like to know what I do wrong Pleae let me know if you have sugestions Thank you Wiljan - Altera_Forum
Honored Contributor
Hi
And now a bit more progress... I did install the Nios and Quartus II v 7.1 on my XP Nios part compiled fine as in 8.2 and now so did the Quartus part... After 1H 36M and it did compile without Error :) Now I did make a small change to the top evel design so I expected the video to all 3 hannels to come from input 1 Hit start compiling...... 1H36 minuttes later no error and I did download againg to the Cyclone III and loaded the soft from Nios... black screen :( It seems imposible to me to do develomping if I have to wait so long time after every change to see if it work or not So there must be some adjustment which make this compilation quicker... so the design are not optimized for picoSeconds.... any hint? Also I do still look for hints to rotate the video 90 deg Please let me know if you have ideas Wiljan - Altera_Forum
Honored Contributor
hello wiljan,
thanks for posting pictures of your project, its neat to see what people are doing. incremental compile should be able to shorten your compile times. can you post more from your compilation you posted on January 24th, 2009, 09:31 AM? i can't see the actual errors. - Altera_Forum
Honored Contributor
Hi
thepancake thank you for feedback here you have the error log from Quatrus II 8.1 on my Vista PC I would realy hope I can work on this PC since it's quad core and pretty fast compared to my XP laptop Error: wrong# args: should be "post_sdc_message msg_type msg" while executing "post_sdc_message -type critical_warning "Could not find correct number of DQ pins for DQS pin $i. Found [llength $dq_p] pins. Expecting 8." " (procedure "get_ddr_pins" line 15) invoked from within "get_ddr_pins $instname pins" (procedure "add_requirements_for_instance" line 16) invoked from within "add_requirements_for_instance $corename $inst t $ddr2_32bit_phy_use_high_performance_timing" ("foreach" body line 3) invoked from within "foreach inst $instance_list { post_sdc_message info "Adding SDC requirements for $corename instance $inst" add_requirements_for_instance $corename $..." (file "ddr2_32bit_phy_ddr_timing.sdc" line 365) Error: Can't fit design in device Error: Quartus II Fitter was unsuccessful. 2 errors, 23 warnings Error: Peak virtual memory: 324 megabytes Error: Processing ended: Tue Jan 27 21:00:25 2009 Error: Elapsed time: 00:00:14 Error: Total CPU time (on all processors): 00:00:14 Error: Quartus II Full Compilation was unsuccessful. 4 errors, 248 warnings If you like you can try yourself ... grab the code here http://www.bitec.ltd.uk/outgoing/bitec_hsmc_quad_video_28mar08.zip Best regards Wiljan - Altera_Forum
Honored Contributor
looks like problems in the sdc file associated with the DDR memory.
try looking at the Quartus release notes: http://www.altera.com/literature/rn/rn_qts.pdf search for the following line: "The SDC and Tcl scripts generated in Quartus II software versions". you should just need to regenerate the DDR cores in Quartus 8.1. - Altera_Forum
Honored Contributor
Hi
@ thepancake, thank you Now the Quartus 8.1 do do compile totaly :) on my Vista PC in 15m 22s quite some big difference. I do still have 1 problem on my Vista setup. In Quartus II 8.1 I can start the Quartus programmer and download the sof all works fine When I use the Nios 8.1 have some soft I want to test on the board you typical say "run on Nios hardware" With the Sof file in place I only see the app resets not doing any changes which are in the software. If I try start the Quartus Programmer from the "Tools" in the Nois software I get a prograsbar saying "Initializing the Quartus II programmer" ... Hanging forever at 30% or so..... I did never see this in XP Any good ideas? btw. I still need a good idea how to rotate the video... anyone? Wiljan - Altera_Forum
Honored Contributor
15 minutes compared with 1 hour and 36 minutes? that's great.
i don't know about the NIOS problem. rotating the pixels you'll probably need to write some HDL. if you do it right you can use it in SOPC builder. rotation of an image is "just" an address remap. some good planning and a couple of counters should do it. ;) - Altera_Forum
Honored Contributor
Thepancake
The Nios problem have to wait a bit... I can easy do some testing whan I use Quartus now I have realy tried to understand a way to do some rotating but I'm still stucked. The video goes to the FIFO which does hold 1 line of RGB then the DMA do transfer it to the RAM ....but I do not see a way to tell it to put data on every 640*X instead of a block (row) from the pointer I also didi think of making 2 counters and just read 1 byte at a time and put it where it need to go... but I belive thes will way to slow If you have more details it would be great Wiljan