Cyclone® IV 　SDR SDRAM DDR2 Timing Parameter Settings

Hi Pochi,

Which document that you have referred to?

Which IP that you used for SDR? is it SDR or DDR?

Regards,

Adzim

Dear Adzim

Thank you for your comment.

Sorry for the mixed information.
I will use SDR.

I looked at the document “Interfacing DDR SDRAM with Cyclone Devices” but could not find the individual timing parameters or timing charts for SDR.

Best Regards,

Pochi

Hi Pochi,

Thanks for your feedback.

I think you might want to look at the sdram controller document in this link: https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/sdram-controller-core.html

Since sdram controller is using avalon transfer, you can refer to avalon interface specification from this link: https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/typical-read-and-write-transfers.html

Regards,

Adzim

Hi Pochi,

I think the timing setting should be refer to memory datasheet of your memory component.

For example, in page 32 shows electrical characteristics for the memory component in this link: https://www.alldatasheet.com/datasheet-pdf/view/75877/MICRON/MT48LC4M32B2.html

Regards,

Adzim

Hi Pochi,

I may not understand your question at this point. The setting is to define the memory characteristics.

So, it's limit to what memory has been used.

I don't think the FPGA has that information.

You may clarify your question if I'm not answering your question.

Besides, which IP that you are using and Quartus version?

Regards,

Adzim

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