New Contributor
Regular ContributorHi Pochi,
Thanks for your feedback.
I think you might want to look at the sdram controller document in this link: https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/sdram-controller-core.html
Since sdram controller is using avalon transfer, you can refer to avalon interface specification from this link: https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/typical-read-and-write-transfers.html
Regards,
Adzim
New ContributorHi Adzim,
Thanks to you, I was able to get most of the information I wanted.
I would like to have the following additional information.
What is the range of the following FPGA settings or characteristics?
1. Output Data High Impedance Time(tHZ)
2. Transition Time of CLK ※Rise and Fall (tR,tF)
3. Data-in Set-up Time(tDH)
4. Data-in Hold Time(tDS)
5. Address hold Time(tAH)
6.CKE Hold Time(tCKH)
7.Exit self refresh to ACTIVE command(tXSR)
Best Regards,
Pochi
