Cyclone® IV 　SDR SDRAM DDR2 Timing Parameter Settings

Hi Pochi,

Thanks for your feedback.

I think you might want to look at the sdram controller document in this link: https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/sdram-controller-core.html

Since sdram controller is using avalon transfer, you can refer to avalon interface specification from this link: https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/typical-read-and-write-transfers.html

Regards,

Adzim