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Pochi's avatar
Pochi
Icon for New Contributor rankNew Contributor
1 year ago

Cyclone® IV 　SDR SDRAM DDR2 Timing Parameter Settings

I found a document for DDR2 timing parameter settings, but I can't find anything for SDR. I would like to know the setting values of each parameter, so I would appreciate it if someone could help me....
Fpga Devkit
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi Pochi,


I may not understand your question at this point. The setting is to define the memory characteristics.

So, it's limit to what memory has been used.

I don't think the FPGA has that information.

You may clarify your question if I'm not answering your question.


Besides, which IP that you are using and Quartus version?


Regards,

Adzim


  • Pochi's avatar
    Pochi
    Icon for New Contributor rankNew Contributor
    1 year ago

    Hi Adzim,

    I was able to the information I wanted.

    Thanks.

    Best regards,

    Pochi