clock gate conversion issue

Hi

My FPGA desgin is prototype which use for ASIC RTL ,

Part of my desgin includes clock gate which choose 1 clock from several synchronized clocks (generated from same source clock )

Additionally, the clock gate instance includes a solution for glitch clock by enabling/disabling the clock at the falling edge (using a NOT logic element) :

The current synthesis & mappin are performed by Synplify Premier tool and P & R by Quartus ( version 22.3 )

The clock gate solution is :

Same clock for all the FF's enabling the selection of the appropriate rate via a multiplexer (mux).

Regarding the glitch mux soultion which has 'not' logic element - Synplify Premier create a new output clock from the PLL referred to as <clock_name>_inv_proxy and create relevant constraint for Quartus - all these worked fine without any timing issues ,

Now I'd like to do all the process in Quartus ( for same design )

Quartus doesn't automatically generate a new inverted clock from the PLL. Instead, it retains the 'not' logic element."

this status cause to setup vilolation since the clock routing is as other logic elements routing

please advice