Forum Discussion
ymiler
Contributor
Contributorclock gate conversion issue
Hi My FPGA desgin is prototype which use for ASIC RTL , Part of my desgin includes clock gate which choose 1 clock from several synchronized clocks (generated from same source clock ) Additional...
ShengN_altera
Super Contributor
Super ContributorSure, will wait for the minimal test case.
ymilerContributor
ContributorHi
For the beginning, I create a test case with minimal design:
PLL - > clock gate -> counter (with no inverse clock)
I have the flag :
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
Why Quartus did not convert the clock gate?
