Forum Discussion
ymiler
Contributor
Contributorclock gate conversion issue
Hi My FPGA desgin is prototype which use for ASIC RTL , Part of my desgin includes clock gate which choose 1 clock from several synchronized clocks (generated from same source clock ) Additional...
sstrell
Super Contributor
Super ContributorCan't you just invert the clock in the PLL output settings?
Side note: none of what you mentioned is recommended for FPGA design (latches and gated clocks), though you do mention this is for prototyping an ASIC design.
- ymiler
There are 2 paths for same output source clock
1) posedge edge ( FF's )
2) negedge edge ( for glitchless mux code )
If I simply invert the PLL clock, I can change the functional code
Synplify Premier didn't change the functionality by adding 1 more output clock from PLL ( specific to glitch mux code ) and removing the 'not' gate in the "glitch mux" code
