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ymiler's avatar
ymiler
Icon for Contributor rankContributor
2 years ago

clock gate conversion issue

Hi My FPGA desgin is prototype which use for ASIC RTL , Part of my desgin includes clock gate which choose 1 clock from several synchronized clocks (generated from same source clock ) Additional...
Fpga Devkit
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,

You need this further assignment set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION_BASE_CLOCK ON -entity bonsai_top

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  • ymiler's avatar
    ymiler
    Icon for Contributor rankContributor
    2 years ago

    Indeed , It's working !!

    Thanks

    Now , I added 1 more clock gate .

    Meaning the output clock of CG A is connecting to CG B input clock

    ( attached new archive file )

    I have same case in my prototype RTL release

    In this case , Quartus didn't convert the clock gates

    please advice