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ymiler's avatar
ymiler
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1 year ago

clock gate conversion issue

Hi My FPGA desgin is prototype which use for ASIC RTL , Part of my desgin includes clock gate which choose 1 clock from several synchronized clocks (generated from same source clock ) Additional...
Fpga Devkit
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,


How about adding clock inversion primitive from PLL to glitch mux which has 'not' logic element?


Thanks,

Regards,

Sheng


ymiler's avatar
ymiler
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1 year ago

This is an option, but I prefer to do not change the code manually.

The preferred option is for the tool to be able to solve the problem on its own