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ymiler's avatar
ymiler
Icon for Contributor rankContributor
2 years ago

clock gate conversion issue

Hi My FPGA desgin is prototype which use for ASIC RTL , Part of my desgin includes clock gate which choose 1 clock from several synchronized clocks (generated from same source clock ) Additional...
Fpga Devkit
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,


When you cascade CG A and CG B, it forms a gated clock tree. Latch (CPEN) is an unsupported gate in the gated clock tree. May be can use flip-flop or combinational logic for the clock gating cascading.


Thanks,

Regards,

Sheng