clk input 50 MHz to pinE13 CycloneIII dev kit

Hi all learned members of the forum,

I am writing a Verilog code to drive the 7-segment user display using clock signal to count 0 to 3 while selecting inputs from mux to selectively drive each digit of the 4-digit 7-segment display. This is part of my getting to know the board as well as learning digital concepts. In Modelsim and testbench, it's ok.

My board: http://www.altera.com/products/devkits/altera/kit-cyc3.html

My problem:

Q1.) In the pin assignment, I narrowed down my option for clock to what I think is the simplest option. The 50 Mhz oscillator. The reference manual says signal propagates to pin E13 of the FPGA. But when I do "pin assignments", pin E13 does not exist in the list. Why? Did I miss something?

Q2.) Because I could not get the 50 Mhz clk, I decided to use the 125 Mhz on board clk. But when I compile, there is this critical warning "found minimum pulse width or period violations". I guess my counter is counting too fast? Becuase when I implemented just the counter module, the same error message occurred.

If so, please mention/point to me a technique to get the counter to count slower which I can try to implement.

Thank you very much.