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Altera_Forum
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17 years ago

clk input 50 MHz to pinE13 CycloneIII dev kit

Hi all learned members of the forum, I am writing a Verilog code to drive the 7-segment user display using clock signal to count 0 to 3 while selecting inputs from mux to selectively drive each...
Altera_Forum's avatar
Altera_Forum
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17 years ago

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The reference manual says signal propagates to pin E13 of the FPGA.

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I see, that this is written in the manual. Actually E13 is a VCCIO8 pin. You may ask Altera for a correct version of the reference manual.

P.S.: According to the schematic, CLKIN_50 is to PIN_AH15. There's also a cycloneIII_3c120_dev_quartus_pinouts example, that contains most relevant pinouts.