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Altera_Forum's avatar
Altera_Forum
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17 years ago

clk input 50 MHz to pinE13 CycloneIII dev kit

Hi all learned members of the forum, I am writing a Verilog code to drive the 7-segment user display using clock signal to count 0 to 3 while selecting inputs from mux to selectively drive each...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Thank you.

For beginner, this can be confusing.

But at least now I know I can check the pin info in ref manual against the schematics.