C4GX kit dev + TSE without external memory

Hi all,

I got a new mistake.

I start with the board update portal design from altera.

I don't understand why in this design there is a big onchip memory and SSRAM.

Can someone explain me how does it work.

Is the code loaded in the onchip memory to the SSRAM?

The SGDMA's are writting directly to the big onchip memory or SSRAM ?

I would like to modify it and use the design without external memory.

But I try to had an onchip memory to replace the SSRAM.

But It doesn't work.

In SOPC in NIOS I've got the vector interruption adresses at my onchip memory adress + 0x120 offset.

My hex files from nios SBT is 379 bytes larger.

I would like to have an exemple of SOPC configuration and BSp linker adresses (SBT tools).

I'am lost.

Thanks for help.