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Altera_Forum's avatar
Altera_Forum
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14 years ago

C4GX kit dev + TSE without external memory

Hi all, I got a new mistake. I start with the board update portal design from altera. I don't understand why in this design there is a big onchip memory and SSRAM. Can someone explain...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

It looks like it's setup properly... it could be a good idea to put some Signaltap probes all around the SGDMA to check up what it is doing.