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Altera_Forum
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14 years ago

C4GX kit dev + TSE without external memory

Hi all, I got a new mistake. I start with the board update portal design from altera. I don't understand why in this design there is a big onchip memory and SSRAM. Can someone explain...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi all,

I was very busy and know i can share you my little experience.

I ask to the altera support and the response is not very accurate.

In according to altera support is better to don't use QSYS and when you start from an design example to don't modify the SOPC system even if you don't use some peripherals.

For me it works but the response it is not what I expect.

thanks.