[Arria10] (mSGDMA <=> PCIE_Hip_Txs) txs_waitrequest signal show "big delay" when reading operation

hello expert,

On our own Arrria10 board, we use "PCIE gen3x8 with AVMM-DMA (64bit)" setting.

Per our system specific scenario, we have to add "MSGDMA + TSE " for ethernet i/f. But we met a "Txs_waitRequest_o deassert has too big delay " problem , detail as following :

[1] let's talk that marked number (3) in above picture, [Hip_Txs] connects to [TSE_subsystem -> dma_rx_mm_write] , which is the ethernet packet receiving path.

Firstly this recv path work fine as expect. From SigTap picture(below), we see per around ~10 clock cycles, "Txs_waitrequest" signal was deasserted to activate the mSGDMA write data through "Hip_Txs" into Host memory space. thus ethernet were transfered from fpga tse sub-system into Host memory correctly, and the transferring performance is correct.

【2】unfortunately for the Ethernet XMit path, where [TSE_subsystem -> dma_tx_mm_read] connects to [Hip_Txs], the performance is very bad. From SigTap picture (below), we found per around ~168 clock cycles, "Txs_waitrequest" signal was deasserted to activate the mSGDMA read data through "Hip_Txs" from HOST (x86 cpu). 【168 cycles】 is TOO BIG delay between every mSGDMA reading operation, thus the result is " the sending performance is very bad".

[Question] : why this big delay (~168 cycles) of "Txs_waitrequest" happens in mSGDMA reading direction? while the reverse writing direction the "Txs_waitrequest" behaviour good ?

[BTW], we uses "AVMM-DMA" setting in our system. We made an experiment to change from "AVMM-DMA" to "AVMM w/o DMA" in PCIe HIP core, in this case both "mSGDMA writing" and mSGDMA reading works fine, that says the “~168 cycles delay" disappears, this maybe some clues for your expertised analysis.