Forum Discussion

Contributor

4 years ago

[Arria10] (mSGDMA <=> PCIE_Hip_Txs) txs_waitrequest signal show "big delay" when reading operation

hello expert, On our own Arrria10 board, we use "PCIE gen3x8 with AVMM-DMA (64bit)" setting. Per our system specific scenario, we have to add "MSGDMA + TSE " for ethernet i/f. But we met a "Txs...

JET60200

Contributor

4 years ago

@SengKok_L_Intel ，

hi SK, you'r expert of A10 PCIe HIP Core, would you please help on this issue ?

If need more debugging trace, we can provide.

thanks very much~

Forum Discussion

[Arria10] (mSGDMA <=> PCIE_Hip_Txs) txs_waitrequest signal show "big delay" when reading operation

Recent Discussions

SyncE clock as the reference for DDR, HBM, and FPGA control interfaces in the Agilex M-Series design

PCIe Root Complex on DK-A5E013BM16AEA

Agilex™ 7 FPGA M-Series Development Kit_HBM2e Edition_REVB2_Altera

Agilex 7 R-Tile PIPE Direct endpoint receives Set_Slot_Power_Limit, but no Config TLPs

R-tile CXL base hard IP example for the Agilex 7 M-series Dev Kit (DK_DEV_AGM039EA) does not work