KhaiChein_Y_Intel
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Re: agilex 5 lpddr4 connection
Hi Dany, As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. Thanks. Best regards, Khai617Views0likes1CommentRe: agilex 5 lpddr4 connection
Hi Dany, Are you looking for the layout file for LPDDR4 in Agilex 5? If yes, please find the user guide here 7.3. LPDDR4 Layout Design Guidelines - https://www.intel.com/content/www/us/en/docs/programmable/817467/24-1-6-1-0/lpddr4-layout-design-guidelines.html 7.1.1. Agilex™ 5 FPGA EMIF IP Parameter for LPDDR4 - https://www.intel.com/content/www/us/en/docs/programmable/817467/24-1-6-1-0/fpga-emif-ip-parameter-for-lpddr4.html 8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning - https://www.intel.com/content/www/us/en/docs/programmable/817467/24-3-1/fpga-emif-ip-pin-and-resource-planning-80533.html Thanks Best regards, Khai672Views0likes0CommentsRe: stratix v dsp fpga board, how to enable aommunication through PCIe edge connector
Hi uzumaki, We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you Best regards, Khai879Views0likes0CommentsRe: stratix v dsp fpga board, how to enable aommunication through PCIe edge connector
Hi uzumaki, I believe I may have misinterpreted your previous message. Please let me know if this is correct. Do you mean that you want to configure the FPGA fabric through the PCIe link and you are looking for a Linux driver for this configuration mode? If this interpretation is correct, you may need to develop your own custom CvP driver for Linux using the sample source code provided for our customer. The sample driver is written in C and can be downloaded from the Configuration via Protocol webpage - https://www.intel.com/content/www/us/en/support/programmable/support-resources/configuration/cfg-via-protocol.html. This is the code for an open-source Linux driver to configure the core of an FPGA via CvP. You can use this open-source code as a reference when writing your own driver, or customize this driver to perform CvP operations on your system. Please note that the Linux driver provided by Intel is not a production driver. You must adapt this driver to your design's strategy. Should you require assistance with the CVP driver flow, please refer to the detailed instructions provided in this user guide. https://www.intel.com/content/www/us/en/docs/programmable/683889/current/cvp-driver-flow.html Thanks. Best regards, Khai972Views0likes0CommentsRe: stratix v dsp fpga board, how to enable aommunication through PCIe edge connector
Hi uzumaki, After compiling the design and generating the sof file, you have to program the sof file into the Devkit. Programmer showing "no hardware detected" indicates that the JTAG does not detect the hardware connected to it. Please ensure that you have connect the On-Board USB-Blaster II to the board and power on the board. The On-Board USB Blaster allows the configuration of the FPGA using a USB cable which connects directly between the USB port on the board (J7) and a USB port on a PC running the Quartus Prime software. You may find the detailed Board Setup steps in https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/stratix/v-gs.html ( Reference Manual and User Guide ) Thanks. Best regards, Khai1.1KViews0likes1CommentRe: PCIe Linux Driver for Cyclone 10 GX
Hi Mr_Nawaf, The driver for Cyclone 10 GX Avalon Streaming Hard IP for PCIe and Avalon Memory-mapped Interface for PCIe are available in Windows version only. For Cyclone 10 GX FPGA – PCIe* 2.0 x4 DMA reference design, you may find the Linux driver in https://www.intel.com/content/www/us/en/design-example/714945/intel-cyclone-10-gx-fpga-pcie-2-0-x4-dma-design-example.html. After unarchiving the par file, you will see the AN829_driver.tar file in the driver folder. Thanks. Best regards, Khai964Views0likes0Comments