agilex 5 lpddr4 connection

Hi Dany,

Are you looking for the layout file for LPDDR4 in Agilex 5? If yes, please find the user guide here

7.3. LPDDR4 Layout Design Guidelines - https://www.intel.com/content/www/us/en/docs/programmable/817467/24-1-6-1-0/lpddr4-layout-design-guidelines.html

7.1.1. Agilex™ 5 FPGA EMIF IP Parameter for LPDDR4 - https://www.intel.com/content/www/us/en/docs/programmable/817467/24-1-6-1-0/fpga-emif-ip-parameter-for-lpddr4.html

8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning - https://www.intel.com/content/www/us/en/docs/programmable/817467/24-3-1/fpga-emif-ip-pin-and-resource-planning-80533.html

Thanks

Best regards,

Khai