Arria 10 GX dev kit-CvP Functionality

Question

Hi everyone,I’m running into a problem with my Arria 10 GX development kit and hoping someone here can help. I’m trying to get the Configuration via Protocol(CvP) working within the PCIe Hard IP. I am running into trouble when generating the *.periph.jic and *.core.rbf because the configuration device for my dev kit is not present in the options. (Check config_device_options.png)Background:I’m using Quartus Prime Pro (version 19.3) on WindowsThe board is powered correctly and the USB-Blaster II is recognized without issues.The JTAG chain is detected (see jtag_chain.png)Trying to get the .jic into the flash memoryFollowing the user guide for Arria 10 CvP (check ug_a10_cvp_prop.pdf)I am failing at the step when I start the flash over jtag with .jicI’ve double-checked the MSEL pins and confirmed that the board is set to use AS x1 configuration. Any advice or pointers would be appreciated, thank you!

johnt_altera · Answer

Hi,From the description, you have issue splitting the image to periperal jic and core rbf file.May I know if you have recompile your design with CvP enable? Is your Quartus project follow the guide here https://www.intel.com/content/www/us/en/docs/programmable/683871/current/setting-up-the-cvp-parameters-in-device.html?

johnt_altera · Answer

Hi,May I know if you have recompile your design with CvP enable? Is your Quartus project follow the guide here https://www.intel.com/content/www/us/en/docs/programmable/683871/current/setting-up-the-cvp-parameters-in-device.html?Will need this information to further help on debugging the issueThanks

ion_cortex · Answer

Hi,Yes, I already was able to compile with CvP enabled the first time around. The problem I'm having is the specific configuration device on the Arria10 GX dev kit is not shown as an option when I go to convert my .SOF into the .jic and .rbf files. If you refer to the photos, they show what my JTAG chain looks like and the options for the configuration device and you can see that the 5M2210Z FPGA is detected in the chain and flash memory chip, but those aren't options within the other photo for configuration devices.Thank you,Hope this clears up any confusion.

johnt_altera · Answer

Hi,If you are programming the jic file then you should be programming the flash that is connected to the Arria 10 FPGA and not the Max 5 device. Can you check if your MSEL setting on your board is set to Active Serial?You may refer to https://www.intel.com/content/www/us/en/docs/programmable/683227/current/default-switch-and-jumper-settings.html SW4 setting. You will need to set it to 010 as mention in Table 6. The default setting is Passive Serial.Thanks

johnt_altera · Answer

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

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Arria 10 GX dev kit-CvP Functionality

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