Forum Discussion
Hi,
May I know if you have recompile your design with CvP enable? Is your Quartus project follow the guide here https://www.intel.com/content/www/us/en/docs/programmable/683871/current/setting-up-the-cvp-parameters-in-device.html?
Will need this information to further help on debugging the issue
Thanks
Hi,
Yes, I already was able to compile with CvP enabled the first time around. The problem I'm having is the specific configuration device on the Arria10 GX dev kit is not shown as an option when I go to convert my .SOF into the .jic and .rbf files. If you refer to the photos, they show what my JTAG chain looks like and the options for the configuration device and you can see that the 5M2210Z FPGA is detected in the chain and flash memory chip, but those aren't options within the other photo for configuration devices.
Thank you,
Hope this clears up any confusion.