Agilex™ 5 FPGA E-Series 065B Premium Development

Hi,
information in your post is rather scarce. Can you give a brief sketch of intended clock topology? GTL transceiver system PLL can generate a core clock, but only if respective transceiver IP is instantiated. They can't work as standalone PLL like IO-PLL. They have to be instantiated using GTS System PLL Clocks Intel FPGA IP.

Iam attaching the schematic of Agilex™ 5 FPGA E-Series 065B Premium Development board.

Nme : agilex5e_065b_premium_devkit_es_rev3.pdf

In this board two single end clock available 100 Mhz,125 Mhz.But using this clocks I can't create 491.52 Mhz clock. Only using 153.6 Mhz or 184.32 Mhz can create 491.52 Mhz and these clocks pins are differential only. But when I using this iam getting error.

Hi,

153.6 MHz differential clock from the development kit schematic is used for transceiver banks. I don't think you can use it for core fabric unless you are using System PLL. You can check this link if you wanted to use system PLL for core logic:

https://www.intel.com/content/www/us/en/docs/programmable/817660/25-1-1/system-pll-clock-for-fpga-core.html

Regards,

Aqid

Hi,

I wish to follow up with you regarding this case. Do you have any updates?

Regards,

Aqid

Now the problem is resolved. I tried using BTS(board test system) clock controller tool. By using this we can create the clocks and this we can assign to clock pin.

https://www.intel.com/content/www/us/en/docs/programmable/814550/current/si5332-clock.html

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.