Agilex™ 5 FPGA E-Series 065B Premium Development

Hi,

153.6 MHz differential clock from the development kit schematic is used for transceiver banks. I don't think you can use it for core fabric unless you are using System PLL. You can check this link if you wanted to use system PLL for core logic:

https://www.intel.com/content/www/us/en/docs/programmable/817660/25-1-1/system-pll-clock-for-fpga-core.html

Regards,

Aqid