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Sarath_K_S's avatar
Sarath_K_S
Icon for New Contributor rankNew Contributor
4 months ago

Agilex™ 5 FPGA E-Series 065B Premium Development

I am using Agilex™ 5 FPGA E-Series 065B Premium Development and For my project I required 491.52 MHz clock. when I checked the schematic of the development board,one 153.6 MHz differential clock ava...
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FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
4 months ago

Hi,
information in your post is rather scarce. Can you give a brief sketch of intended clock topology? GTL transceiver system PLL can generate a core clock, but only if respective transceiver IP is instantiated. They can't work as standalone PLL like IO-PLL. They have to be instantiated using GTS System PLL Clocks Intel FPGA IP.