about Spansion flash

I can probably work you up a simple example design that you can just run but you'll have to bare with me as I can only work it in between other things. If I can't get it to you today then perhaps tomorrow.

Jake

Hi,

the shipped ethernet interface test project enet_loopback did not work on my board. When i oppened the sopc system using quartus 8.0 sp1 it was reported that the component md_cfg_interface_v3_0 is missing. I have created service request to altera and have not got any response yet. That's why i turned to the simple socket server exampe for ethernet interface test.

and to Jake, i would really appreciate it if you could send me some test program.

Okay give this is a shot. It runs on my board. This example uses the Avalon OpenCores 10/100 Ethernet MAC rather than the Altera TSE MAC.

I've included the SOF file in the ZIP file so you can just program it but you'll want to recompile the project to see how it's structured. I couldn't include the database files for size.

In order to recompile you'll also need the Avalon OpenCores MAC which is available here:

http://www.alteraforum.com/forum/showthread.php?t=3665

You'll need to unzip this in the c:\altera\80\ip\sopc_builder_ip\ folder.

As far as the software goes. I've hard-coded the MAC address and set the static IP address to 192.168.1.50.

So to run it, you'll need to program the SOF into the board, then use the IDE to download and run the simple-socket server example. This example is running out of the SSRAM on the board.

Jake

Hi Jake,

Thank you so much for the example! I have tested it on my board and it works fine! So now i can compare your design example with mine and try to understand what i have done wrong. I have not re-compiled your design yet so i may bother you in the future ... Many thanks.

Hi Jake,

Do you know how to tune the ethernet opencore parameters to remove the timing issue? Now i have the timing warnings concerning eth_rx_clk. Thank you in advance.

You'll need to be more specific. What paths are failing timing on the RX path?

Jake

Hi Jake,

This is what i got in messages.

Critical Warning: Timing requirements not met

Info: Worst-case hold slack is -0.588

Info: Slack End Point TNS Clock

Info: ========= ============= =====================

Info: -0.588 -0.588 eth_rx_clk

Info: 0.041 0.000 eth_tx_clk

Info: 0.341 0.000 clk_fpga

Info: 0.341 0.000 clk_sopc

Info: 0.341 0.000 io_clk

Info: 5.421 0.000 ssram_clk_int

Info: 9.500 0.000 n/a

and i use your .sdc file for the timing setting.

Can you send me your archived project? In the meantime, I would assume you can ignore the issue.

Jake

Hi Jake,

If you get the time check the archived project which is pretty much the same as your reference design. Although there is timing warning the design works. But it seems that the eth_rx_clk, eth_tx_clk should be fine tuned concerning timing constraints if i want to use the opencore and add some other big logic blocks.

Hi Jake,

I have a question about the .sdc file. Sentences like

set_clock_latency -source -early 0.9 [get_clocks {eth_tx_clk}]

set_clock_latency -source -late 1.2 [get_clocks {eth_tx_clk}]

set_clock_latency -source -early 0.97 [get_clocks {eth_rx_clk}]

set_clock_latency -source -late 1.3 [get_clocks {eth_rx_clk}]# Input delays

set_input_delay -clock [get_clocks {clk_sopc}] 0.000 [get_ports {enet_mdio}]

set_input_delay -clock [get_clocks {eth_rx_clk}] -max 10.40 [get_ports {enet_rx_col enet_rx_crs enet_rx_dv enet_rx_er enet_rxd*}]

set_input_delay -clock [get_clocks {eth_rx_clk}] -min 10.90 [get_ports {enet_rx_col enet_rx_crs enet_rx_dv enet_rx_er enet_rxd*}]

are they design-specific or can be used in general case?