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DanielGP's avatar
DanielGP
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5 years ago

40Gbps Ethernet MACPHY IP Hardware Demo Design using QSFP

Hello!

I am trying to test the 40Gbps Demo for Stratix V in Quartus 18.1 Standard Edition. After compiling the project, I get the following error, even though the target device is right:

Error (12252): Invalid device family 'Stratix V' specified

Also, when I open the gen_40 IP, it does not let me insert the Device Family (stuck to Unknown).

Am I doing anything wrong? The example design seems to have been prepared for Quartus 15.0. That might be part of the problem?

Thanks.

13 Replies

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    You can use the design as the starting point and then migrate/port over the design to the board that you intend to test.


    Regards -SK


    • DanielGP's avatar
      DanielGP
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      5 years ago

      Hi, again!

      Thank you for all the support. I am still struggling a bit here.

      One question I need to be sure of. For the Stratix V GX Development Kit, we have a 40G QSFP connector that uses 4 transceiver channels. Is it really possible to use only one channel, i.e., having only one independent 10Gb connection?

      I thought I could use this cable to have 1 to 4 independent channels but I cannot find any example to do that. Is it really possible?

      Regards.

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    Are you downloading the v17.1 design file, refer to the link below?

    https://www.intel.com/content/dam/altera-www/global/en_US/uploads/1/1c/Alt_eth_40G_qsfp_171.zip


    After unzipping the file, you can open the .qar in v18.1std. From the Project Navigator, select IP components, double click the “gen_40” to open the IP GUI, and then generate it (if you would like to upgrade to v18.1std).


    It works well from my site. You may probably try it by using v17.1std as well.


    Regards -SK


    • DanielGP's avatar
      DanielGP
      Icon for New Contributor rankNew Contributor
      5 years ago

      Hi, thank you for the fast reply.

      Just to be sure, I downloaded again the example design from the link you provided (indeed, version 17.1, not 15.0 as announced in the tutorial page).

      After opening the .qar in v18.1 and opening the gen_40 IP GUI, i am still not able to generate the IP as you can see below:

      Is it a license issue? I have enabled the one-year license from recently acquiring the Stratix V Development Kit.

      Thank you.

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago
    1. Do you able to instantiate a new 40G/100G Ethernet Intel FPGA IP from the IP catalog?
    2. Do you able to create an empty project by selecting this device 5SGXEA7K2F40C2?


    Regards -SK


    • DanielGP's avatar
      DanielGP
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      5 years ago

      1) Yes but only in a different project as you can check below:

      2) Yes, I have already tested a few projects before. Recently, I tested the one with the your TSE IP and now I want to do the same but for 10Gbps Ethernet. Is there other option rather than this 40Gbps IP? What I need are two 10Gbps ethernet connections...

      Thank you for the attention!

      • SengKok_L_Intel's avatar
        SengKok_L_Intel
        Icon for Regular Contributor rankRegular Contributor
        5 years ago

        If you can instantiate a new IP without a problem, then you can try to work around it by using the following settings to generate the 40G IP. If not, you might need to use v17.1std.

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    The protocol spec for 40G is not the same as 10G, which means, you can't use a single 40G Ethernet IP as four individual 10G ethernets. In this case, you should use two 10Gpbs IP.



    Regards -SK


    • DanielGP's avatar
      DanielGP
      Icon for New Contributor rankNew Contributor
      5 years ago

      Ok, that was exactly my question, thanks.

      In that case, I will not concern with the 40Gbps IP problem anymore.

      Now, for the 10G, is there another example design for the stratix V development board I could follow? The one you posted above is for the Transceiver Signal Integrity Development Kit and I do not have that one (I even think this one is already discontinued), I have the Stratix V GX FPGA Development Kit.

      Thanks once again!

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    Per my understanding, this is doable. The QSFP ports can use as four independent 10G channels.


    Regards -SK


  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    I will set this forum case to close-pending for now. The status will remain in this state for 15 calendar days, simply post a note in this forum and it will be reopened for further investigation.