Forum Discussion
Occasional ContributoroneAPI on Cyclone10gx
Hi all,
the official Intel fpga requirement page says the Cyclone10gx fpga is supported by oneAPI so I downloaded the latest version on my Ubuntu20 (Quartus Prime also installed), I tried to compile a sample-adder, the compiler (targeting the fpga) works but then when I run simple-add-buffer.fpga I get:
tetto@ubuntuoffice:~/simple-add/build$ ./simple-add-buffers.fpga
An exception is caught while computing on device.
terminate called after throwing an instance of 'sycl::_V1::runtime_error'
what(): No device of requested type available. Please check https://software.intel.com/content/www/us/en/develop/articles/intel-oneapi-dpcpp-system-requirements.html -1 (PI_ERROR_DEVICE_NOT_FOUND)
Aborted (core dumped)
43 Replies
BoonBengT_AlteraModerator
Hi @StefanoC,
Good to know that the emulation are successful, hence that should tell us that the required component/libraries might be correctly available.
As for the hardware compilation suspecting there might be some lower caps on the 'gx' which is causing some problem.
Would suggest to try with 'Cyclone10GX'.
If that does not work, maybe you can try with the full compilation command instead as below:
- icpx -fsycl -fintelfpga -DFPGA_HARDWARE -I../../../../include vector_add.cpp -Xshardware -Xstarget=Cyclone10GX -o vector_add.fpga
And for the hardware compilation from your end, is the build completed successfully with the bitsteam file generated? Is there a .prj folder generated?
Regards
BB
StefanoCWhile the part1 works, I could compile and run it (although not without the make command but with the full command you shared), part2 does NOT work. Part1 is not interesting after all as it's the CPU that is doing the calculation, part2 is where I am mostly interested because the fpga does something. And interestingly enough the error I get is probably the very same I always had in the first place when I started this thread (PI_ERROR something..).
See below the issue with part2 (also the other abnormal thing is the cout that prints: "Running on device: SimulatorDevice" since given the compiler flag FPGA_HARDWARE it shouldn't say SimulatorDevice (unless something is wrong with the Cyclone10GX driver/oneAPI hardware support?
tetto@ubuntuoffice:~/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/part2_dpcpp_functor_usm/src$ icpx -fsycl -fintelfpga -DFPGA_HARDWARE -I../../../../include vector_add.cpp -Xshardware -Xstarget=Cyclone10GX -o vector_add.fpga aoc: Compiling for FPGA. This process may take several hours to complete. Prior to performing this compile, be sure to check the reports to ensure the design will meet your performance targets. If the reports indicate performance targets are not being met, code edits may be required. Please refer to the oneAPI FPGA Optimization Guide for information on performance tuning applications for FPGAs. tetto@ubuntuoffice:~/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/part2_dpcpp_functor_usm/src$ tetto@ubuntuoffice:~/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/part2_dpcpp_functor_usm/src$ ls -lrt total 680 -rw-rw-r-- 1 tetto tetto 3166 Feb 5 12:52 vector_add.cpp -rw-rw-r-- 1 tetto tetto 6348 Feb 5 12:52 CMakeLists.txt drwxrwxr-x 11 tetto tetto 4096 Feb 7 21:06 vector_add.fpga.prj -rwxrwxr-x 1 tetto tetto 679176 Feb 7 21:06 vector_add.fpga tetto@ubuntuoffice:~/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/part2_dpcpp_functor_usm/src$ ./vector_add.fpga Running on device: SimulatorDevice : Multi-process Simulator (aclmsim0) add two vectors of size 256 Caught a SYCL host exception: Invalid device program image: size is zero -30 (PI_ERROR_INVALID_VALUE) terminate called after throwing an instance of 'sycl::_V1::runtime_error' what(): Invalid device program image: size is zero -30 (PI_ERROR_INVALID_VALUE) Aborted (core dumped) tetto@ubuntuoffice:~/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fpga_compile/part2_dpcpp_functor_usm/src$
yuguenHey Stefano,
When you compile using an FPGA family (such as "Cyclone10GX"), the compiler enters an HLS flow: it only generates an IP that you need to manually integrate into your own RTL pipeline.
The fpga binary that you obtained is not executable: it is only produced for you to inspect the performance of the IP after quartus compiled it (fmax, resource usage, etc.)
Here is a code sample demonstrating how one can integrate an HLS IP into an RTL pipeline to be able to run such IP on an FPGA: https://github.com/oneapi-src/oneAPI-samples/tree/master/DirectProgramming/C%2B%2BSYCL_FPGA/Tutorials/Tools/platform_designer
You were expecting the compiler to produce a binary that could be directly executed on the FPGA: to do so, the compiler needs to understand the interface between the IP and your FPGA. This is what we call the "BSP".
Some FPGA board vendors do provide BSPs with their FPGA boards, which would have allowed you to compile your program using "icpx ... -Xstarget=<path to your BSP> ..." rather than "-Xstarget=Cyclone10GX".
In that case, and in that case only, the FPGA binary produced could have been run on the FPGA natively.
You can have a look at this documentation page to better understand the difference between the "FPGA acceleration flow" and the "HLS flow": https://www.intel.com/content/www/us/en/docs/oneapi-fpga-add-on/developer-guide/2024-0/intel-oneapi-fpga-development-flow.html
- StefanoC
@yuguen that really clarified everything, thanks!
In the document you pointed:
something is unclear to me, you create a project in Quartus but it seems you do not create a Top-level entity, since when I do "Start Analysis and Elaboration" I get an error about that, I wonder if a top-level entity should be created anyway and what should look like. In one screenshot from the previous github I see that the top level entity is named "add" when you create the project, but then nothing is mentioned about it (what should just contain?)
- yuguen
Hey @StefanoC
This sample demonstrates how to integrate a generated IP into an existing RTL pipeline.
In this case, the existing RTL files are located in https://github.com/oneapi-src/oneAPI-samples/blob/master/DirectProgramming/C%2B%2BSYCL_FPGA/Tutorials/Tools/platform_designer/add-quartus-sln
The "add" top level entity is found in the add.sv file.
"Step 2." tells you to copy this "add.sv" file into your Quartus project folder:
cp add-quartus-sln/add.sv add-quartus
Then, to add it to your Quartus project (step 2.v):
Following these steps (with all the other steps), Quartus should be able to understand that the "add" top level module is in this file.
- BoonBengT_Altera
Hi Stefano,
Following through the previous clarification to see if there are any further doubts in regards to this matter.
Hope your doubts have been clarified.
Best Wishes
BB
- BoonBengT_Altera
Hi @StefanoC,
Greetings, as we do not receive any further clarification/updates on the matter, hence would assume challenge are overcome. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. For new queries, please feel free to open a new thread and we will be right with you. Pleasure having you here.
Best Wishes
BB
- StefanoCForgot to say that Cyclone10gx is not mentioned in the previous niosV thing, as you indicated that link, shall I assume that approach will work on my board?
