StefanoC
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simple add fails on stratix10 (USM)
Hi all, on intel devcloud I can compile and run the simple add sample https://github.com/oneapi-src/oneAPI-samples/tree/master/DirectProgramming/C%2B%2BSYCL/DenseLinearAlgebra/simple-add/src the issue is that the "buffer" version works, compiles and runs ok, while the USM version does not. the USM version is compiled with this: cmake .. -DFPGA_DEVICE=/glob/development-tools/versions/oneapi/2024.0/oneapi/intel_s10sx_pac:pac_s10_usm -DUSM=1 but at runtime (on the devcloud node fpga_runtime:stratix10) I got this: "Shared memory allocation failure." @yuguen Can you confirm that your sample code is ok to run on the devcloud?Solved1.4KViews0likes3CommentsRe: oneAPI on Cyclone10gx
@whitepau_altera I successfully synthesized the niosV example (as it is), adding this top node: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity test_system is port ( clk : in STD_LOGIC; rst : in STD_LOGIC ); end entity test_system; architecture Behavioral of test_system is component pd_system is port ( clk_clk : in std_logic := 'X'; reset_reset : in std_logic := 'X'; simple_dma_accelerator_device_exception_bus_data : out std_logic_vector(63 downto 0) ); end component pd_system; signal pd_system_clk : std_logic; signal pd_system_rst : std_logic; begin u0 : pd_system port map ( clk_clk => pd_system_clk, reset_reset => pd_system_rst, simple_dma_accelerator_device_exception_bus_data => open ); pd_system_clk <= clk; pd_system_rst <= rst; end architecture Behavioral; However when I tried (a few things) to run the software companion produced by oneAPI I got: tetto@ubuntuoffice:~/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/niosv/kernels/simple_dma/build$ ./simple_dma.fpga Running on device: SimulatorDevice : Multi-process Simulator (aclmsim0) terminate called after throwing an instance of 'sycl::_V1::runtime_error' tetto@ubuntuoffice:~/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/niosv/kernels/simple_dma/build$ tetto@ubuntuoffice:~/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/niosv/kernels/simple_dma/build$ sudo ./simple_dma.fpga [sudo] password for tetto: ./simple_dma.fpga: error while loading shared libraries: libdspba_mpir.so.23: cannot open shared object file: No such file or directory tetto@ubuntuoffice:~/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/niosv/kernels/simple_dma/build$ sudo LD_LIBRARY_PATH=$LD_LIBRARY_PATH ./simple_dma.fpga terminate called after throwing an instance of 'sycl::_V1::runtime_error' what(): No device of requested type available. Please check https://software.intel.com/content/www/us/en/develop/articles/intel-oneapi-dpcpp-system-requirements.html -1 (PI_ERROR_DEVICE_NOT_FOUND) Aborted tetto@ubuntuoffice:~/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/niosv/kernels/simple_dma/build$ Coming back to this example, I was also playing with: https://github.com/oneapi-src/oneAPI-samples/blob/master/DirectProgramming/C%2B%2BSYCL_FPGA/Tutorials/GettingStarted/fpga_compile/part3_dpcpp_lambda_usm/src/vector_add.cpp oneAPI seems to produce a quartus project completed with the top node (that I can compile and synthesize), but again when I run the executable I encounter a runtime error. In that vector_add.src it seems this "unified memory" would just do the job, but I recall you mentioned earlier one has to edit the RTL design (although in this part3 the top node seems properly generated and needed IPs/avalon devices are there and instantiated).4.4KViews0likes1CommentRe: oneAPI on Cyclone10gx
Hi @whitepau_altera I am still running the plain niosv sample simple dma (as it is in the repository without any modification), trying to run in on the hardware and have the cpu (C) interact with the fpga (I confirm the simulation, as detailed in the github repository works). I added this top node entity: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity test_system is port ( clk : in STD_LOGIC; rst : in STD_LOGIC ); end entity test_system; architecture Behavioral of test_system is component pd_system is port ( clk_clk : in std_logic := 'X'; reset_reset : in std_logic := 'X'; simple_dma_accelerator_device_exception_bus_data : out std_logic_vector(63 downto 0) ); end component pd_system; signal pd_system_clk : std_logic; signal pd_system_rst : std_logic; begin u0 : pd_system port map ( clk_clk => pd_system_clk, reset_reset => pd_system_rst, simple_dma_accelerator_device_exception_bus_data => open ); pd_system_clk <= clk; pd_system_rst <= rst; end architecture Behavioral; I synthesized the project onto my board, I got a few warnings: 1) Critical Warning(12677): No exact pin location assignment(s) for 1 pins of 2 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report 2) No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" 3)Timing requirements not met clk -6.334 -18110.791 7371 Slow 900mV 100C Model 1 altera_reserved_tck -1.788 -410.899 380 Slow 900mV 100C Model 2 About 1) I think it's referring to the clock/reset signals, I tried to put clock location in the pin planner as you suggested "C10_CLKUSR" but that value it's not accepted, scrolling the dropdown menu I selected "PIN_C10 I/O Bank 2k"; I haven't yet assigned the reset that's why one location is not assigned. I then used the USB blaster JTAG to program the board (successfully). then I compiled /kernels/simple_dma/ using "make fpga" rather than "make report" and I got an executable, but when I run it I got this: tetto@ubuntuoffice:~/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/niosv/kernels/simple_dma/build$ ./simple_dma.fpga Running on device: SimulatorDevice : Multi-process Simulator (aclmsim0) terminate called after throwing an instance of 'sycl::_V1::runtime_error' what(): Invalid device program image: size is zero -30 (PI_ERROR_INVALID_VALUE) Aborted (core dumped) tetto@ubuntuoffice:~/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/niosv/kernels/simple_dma/build$ sudo env "LD_LIBRARY_PATH=$LD_LIBRARY_PATH" ./simple_dma.fpga terminate called after throwing an instance of 'sycl::_V1::runtime_error' what(): No device of requested type available. Please check https://software.intel.com/content/www/us/en/develop/articles/intel-oneapi-dpcpp-system-requirements.html -1 (PI_ERROR_DEVICE_NOT_FOUND) Aborted I tried with sudo as I suspected it couldn't find the board; I exported a variable because without it could complain about a missing library, however it screams about a runtime error. Am I missing something to run this sample on the board and have the C interact with it? thanks!!4.4KViews0likes0CommentsRe: oneAPI on Cyclone10gx
@whitepau_alterathe simulation does work. I will edit the sample dma to actually do something useful rather than copying/comparing elements. You mentioned I will have to use the nios tools to connect to the soft core; however I was planning on running my code on the computer CPU with some part of my algorithm memory mapped to an IP that will result from oneAPI compiler. So in this case, if I understand correctly, I don't need to connect to the niosV (unless I want to inspect/debug), am I right? thanks!4.5KViews0likes3CommentsRe: oneAPI on Cyclone10gx
@whitepau_altera I think the niosV will fit my case, I will give a try today, one last clarification, as that userguide mention "..demonstrates how to simulate an FPGA IP produced with the Intel® oneAPI DPC++/C++" and scrolling down I see that towards the end it actually "Generate Testbench System". Will I be able to synthetize on the fpga rather than just simulate? thanks! StefanoC4.6KViews0likes8CommentsRe: oneAPI on Cyclone10gx
@whitepau_altera my source code is exactly as the "Naive" solution: https://github.com/oneapi-src/oneAPI-samples/blob/master/DirectProgramming/C%2B%2BSYCL_FPGA/Tutorials/Features/ip_authoring_interfaces/component_interfaces_comparison/naive/src/vector_add.cpp I can compile it with oneAPI and produce IPs; I "just" miss how to how to deal with the avalon thing, as the link below fairly well describes what to do for primitive data type only: https://github.com/oneapi-src/oneAPI-samples/tree/master/DirectProgramming/C%2B%2BSYCL_FPGA/Tutorials/Tools/platform_designer is there an equivalent platform design, module connection for the vectorial add ("naive implementation")? StefanoC4.6KViews0likes10Comments