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Occasional ContributorAI Suite - Spatial IP outputs wrong value
Hello Altera Community
When looking at my Spatial IP in Signal Tap, I can see that it outputs a wrong value. Please help me identify where this mistakes happen.
Below is the Signal Tap result of my test: 3D903C90 - 3D9C3D87 -BD983E38
However from my golden_output_sink_port_0.txt I'm expecting this value: 3D12BC8D - 3DA43E1E - 3DABBE18
Below is the Singal Tap of my input
I'm inserting the values I got from input_vlogkw.txt from the DLA_COMPILER.
Here is a list of warnings I got from Quartus, but they are from proteced sv files that I can't acess:
Warning(16761): VHDL warning at spatial_first.vhd(146): actual for formal port "reset_reset" is neither a static name nor a globally static expression
Warning(13469): Verilog HDL assignment warning at dot_core_controller.sv(381): truncated value with size 6 to match size of target (5)
Warning(16788): Net "out[0][31]" does not have a driver at dsp_sum_of_2n_bf16xbf16.sv(118)
Warning(13469): Verilog HDL assignment warning at dot_core_controller.sv(381): truncated value with size 6 to match size of target (5)
Warning(21620): Design Assistant Results: 1 of 1 High severity rules issued violations in snapshot 'partitioned'. Please refer to DRC report 'C:/Users/mads/Desktop/test/quartus/output_files/spatial_first.drc.partitioned.rpt' for more information
Warning(25315): Some pins are missing drive strength (current strength), termination and/or slew rate assignments. Refer to the I/O Assignment Warnings report for details.
Warning(332158): Clock uncertainty characteristics of the A5EB013BB23BE4SR1 device are preliminary
Warning(18291): Timing characteristics of device A5EB013BB23BE4SR1 are preliminary
Warning(332060): Node: altera_reserved_tck was determined to be a clock but was found without an associated clock assignment.
Warning(332158): Clock uncertainty characteristics of the A5EB013BB23BE4SR1 device are preliminary
Warning(21620): Design Assistant Results: 3 of 34 High severity rules issued violations in snapshot 'final'. Please refer to DRC report 'C:/Users/mads/Desktop/test/quartus/output_files/spatial_first.tq.drc.signoff.rpt' for more information
Attached is Netlist viewer of my Spatial IP.
5 Replies
JohnT_AlteraRegular Contributor
Hi,
Can you guide us on how do you generate the Spatial IP? Please provide the full step so that we can duplicate the issue
- Mads_From_Denmark
To recreate the issue you will need the FPGA AI Suite version 2026.1.1-quartus.
Transfer the the bin and xml files called "fpga_model_spatial_1" to the docker env.
Then execute the following command:
dla_create_ip \
--ip-dir ./ip_repo \
--flow create-ip \
--arch /opt/altera/fpga_ai_suite/ubuntu/dla/example_architectures/AGX5_Simple_Spatial.arch \
--model ./fpga_model_spatial_1.xml
Now in Quartus Prime Pro 26.1, create a now project called "spatial_first". Targeting Agilex5 device A5EB013BB23BE4SR1. Then move the ip_repo folder next to the quartus folder.
Now you will need 4 files,
The Top entity called "spatial_first.vhd"
The QSF config called "spatial_first.qsf"
The system containing the AI model from the ip repo "spatial.qsys"
The signaltaptest.stp to see the signal tap output
The files I have uploaded here on my github, I can also upload the entire project if you will accept that.
https://github.com/madskost/spatial_first
- JohnT_Altera
Hi,
Have you tested on using the system-console to run the application? https://docs.altera.com/r/docs/863373/2026.1.1/fpga-ai-suite-handbook/running-the-hostless-ddr-free-fpga-ai-suite-spatial-ip-design-example
- Mads_From_Denmark
No, I have not tested any of the examples because they all target the premium Agilex 5 E-Series Modular Development Kit, while I only have the DE25 NANO, which is a new device, that does not have support like a GSRD yet.
But it seems like this example is easy to adjust so I will try it out thanks- JohnT_Altera
Yes, it can be easily migrate to DE25 NANO.
